MIPS CPU

Personal Project

I implement a single cycle MIPS processor with SystemVerilog.

Figure 1. The datapath of the single cycle MIPS processor.

In this project, I implement a single cycle MIPS processor (CPU) with SystemVerilog. The processor includes instruction memory, data memory, resisters, arithmetic logic unit (ALU), controller, and jump supporting circuits. The full datapath of the processor is shown in Figure 1. More information can be found in the technical report. My code is also publically available at GitHub.